old_contents: #!/usr/bin/env python
  # Copyright (c) 2015 Angel Terrones (<angelterrones@gmail.com>)
  #
  # Permission is hereby granted, free of charge, to any person obtaining a copy
  # of this software and associated documentation files (the "Software"), to deal
  # inp the Software without restriction, including without limitation the rights
  # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  # copies of the Software, and to permit persons to whom the Software is
  # furnished to do so, subject to the following conditions:
  #
  # The above copyright notice and this permission notice shall be included inp
  # all copies or substantial portions of the Software.
  #
  # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  # AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  # THE SOFTWARE.
  
  from myhdl import Signal
  from myhdl import always
  
  
  class Register:
      def __init__(self,
                   clk: Signal,
                   rst: Signal,
                   we: Signal,
                   i: Signal,
                   o: Signal):
          assert len(i) == len(o), "Input and Output length mismatch"
  
          self.clk = clk
          self.rst = rst
          self.we = we
          self.i = i
          self.o = o
  
      def GetRTL(self):
          @always(self.clk.posedge)
          def rtl():
              if self.rst == 1:
                  self.o.next = 0
              elif self.we == 1:
                  self.o.next = self.i
              else:
                  assert 0, "Invalid register simulation"
  
          return rtl
  
  # Local Variables:
  # flycheck-flake8-maximum-line-length: 120
  # flycheck-flake8rc: ".flake8rc"
  # End:
  
new_contents: #!/usr/bin/env python
  # Copyright (c) 2015 Angel Terrones (<angelterrones@gmail.com>)
  #
  # Permission is hereby granted, free of charge, to any person obtaining a copy
  # of this software and associated documentation files (the "Software"), to deal
  # inp the Software without restriction, including without limitation the rights
  # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  # copies of the Software, and to permit persons to whom the Software is
  # furnished to do so, subject to the following conditions:
  #
  # The above copyright notice and this permission notice shall be included inp
  # all copies or substantial portions of the Software.
  #
  # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  # AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  # THE SOFTWARE.
  
  from myhdl import Signal
  from myhdl import always
  
  
  class Register:
      def __init__(self,
                   clk: Signal,
                   rst: Signal,
                   we: Signal,
                   i: Signal,
                   o: Signal,
                   init=0):
          assert len(i) == len(o), "Input and Output length mismatch"
  
          self.clk = clk
          self.rst = rst
          self.we = we
          self.i = i
          self.o = o
          self.init = init
  
      def GetRTL(self):
          @always(self.clk.posedge)
          def rtl():
              if self.rst == 1:
                  self.o.next = self.init
              elif self.we == 1:
                  self.o.next = self.i
              else:
                  assert 0, "Invalid register simulation"
  
          return rtl
  
  # Local Variables:
  # flycheck-flake8-maximum-line-length: 120
  # flycheck-flake8rc: ".flake8rc"
  # End:
  
subject: Add init value to register.