old_contents: 
  # core rtl constructs
  from core import Block
  from core import PyrtlError
  from core import PyrtlInternalError
  from core import working_block
  from core import reset_working_block
  from core import set_debug_mode
  
  # convenience classes for building hardware
  from wire import WireVector
  from wire import Input, Output
  from wire import Const
  from wire import Register
  from wire import SignedWireVector
  from wire import SignedInput, SignedOutput
  from wire import SignedConst
  from wire import SignedRegister
  
  # helper functions
  from helperfuncs import as_wires
  from helperfuncs import concat
  from helperfuncs import mux
  from helperfuncs import appropriate_register_type
  from helperfuncs import get_block
  from helperfuncs import and_all_bits
  from helperfuncs import or_all_bits
  from helperfuncs import xor_all_bits
  from helperfuncs import parity
  
  # memory blocks
  from memory import MemBlock
  
  # conditional updates
  from conditional import ConditionalUpdate
  
  # block simulation support
  from simulation import Simulation
  from simulation import SimulationTrace
  
  # input and output to file format routines
  from inputoutput import input_from_blif
  from inputoutput import output_to_trivialgraph
  from inputoutput import output_to_verilog
  from inputoutput import output_verilog_testbench
  
  # different analysis and transform passes
  from passes import synthesize
  from passes import optimize
  from passes import area_estimation
  from passes import timing_analysis
  from passes import timing_max_length
  from passes import print_max_length
  from passes import timing_critical_path
  
new_contents: 
  # core rtl constructs
  from core import Block
  from core import PyrtlError
  from core import PyrtlInternalError
  from core import working_block
  from core import reset_working_block
  from core import set_debug_mode
  
  # convenience classes for building hardware
  from wire import WireVector
  from wire import Input, Output
  from wire import Const
  from wire import Register
  from wire import SignedWireVector
  from wire import SignedInput, SignedOutput
  from wire import SignedConst
  from wire import SignedRegister
  
  # helper functions
  from helperfuncs import as_wires
  from helperfuncs import concat
  from helperfuncs import mux
  from helperfuncs import appropriate_register_type
  from helperfuncs import get_block
  from helperfuncs import and_all_bits
  from helperfuncs import or_all_bits
  from helperfuncs import xor_all_bits
  from helperfuncs import parity
  
  # memory blocks
  from memory import MemBlock
  from memory import RomBlock
  
  # conditional updates
  from conditional import ConditionalUpdate
  
  # block simulation support
  from simulation import Simulation
  from simulation import SimulationTrace
  
  # input and output to file format routines
  from inputoutput import input_from_blif
  from inputoutput import output_to_trivialgraph
  from inputoutput import output_to_verilog
  from inputoutput import output_verilog_testbench
  
  # different analysis and transform passes
  from passes import synthesize
  from passes import optimize
  from passes import area_estimation
  from passes import timing_analysis
  from passes import timing_max_length
  from passes import print_max_length
  from passes import timing_critical_path
  
subject: Put the RomBlock in the __init__ file