new_contents: #!/usr/bin/env python3
  
  #
  # This file is part of LiteX-Boards.
  #
  # Copyright (c) 2019-2020 Florent Kermarrec <florent@enjoy-digital.fr>,
  # SPDX-License-Identifier: BSD-2-Clause
  
  import os
  import argparse
  
  from migen import *
  
  from litex_boards.platforms import zynq_xc7z010 
  from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
  
  from litex.soc.interconnect import axi
  from litex.soc.interconnect import wishbone
  
  from litex.soc.cores.clock import *
  from litex.soc.integration.soc_core import *
  from litex.soc.integration.builder import *
  from litex.soc.cores.led import LedChaser
  
  # CRG ----------------------------------------------------------------------------------------------
  
  class _CRG(Module):
      def __init__(self, platform, sys_clk_freq):
          self.rst = Signal()
          self.clock_domains.cd_sys = ClockDomain()
  
          self.submodules.pll = pll = S7PLL(speedgrade=-1)
          self.comb += pll.reset.eq(self.rst)# | platform.request("cpu_reset"))
          pll.register_clkin(platform.request("clk100"), 100e6)
          pll.create_clkout(self.cd_sys, sys_clk_freq)
          platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
          
  # BaseSoC ------------------------------------------------------------------------------------------
  
  class BaseSoC(SoCCore):
      def __init__(self, sys_clk_freq=int(100e6), with_led_chaser=True, **kwargs):
          platform = zynq_xc7z010.Platform()
  
          #if kwargs["uart_name"] == "serial": kwargs["uart_name"] = "usb_uart" # Use USB-UART Pmod on JB.
          kwargs["uart_name"] = "serial"
  
          # SoCCore ----------------------------------------------------------------------------------
          SoCCore.__init__(self, platform, sys_clk_freq,
              ident          = "LiteX SoC on zynq xc7z010",
              ident_version  = True,
              **kwargs)
  
          # CRG --------------------------------------------------------------------------------------
          self.submodules.crg = _CRG(platform, sys_clk_freq)
          
          # Leds -------------------------------------------------------------------------------------
          if with_led_chaser:
              self.submodules.leds = LedChaser(
                  pads         = platform.request_all("user_led"),
                  sys_clk_freq = sys_clk_freq)
  
  # Build --------------------------------------------------------------------------------------------
  
  def main():
      parser = argparse.ArgumentParser(description="LiteX SoC on zynq xc7z010")
      parser.add_argument("--build",        action="store_true", help="Build bitstream")
      parser.add_argument("--load",         action="store_true", help="Load bitstream")
      parser.add_argument("--sys-clk-freq", default=100e6,       help="System clock frequency (default: 100MHz)")
      builder_args(parser)
      soc_core_args(parser)
      vivado_build_args(parser)
      args = parser.parse_args()
  
      soc = BaseSoC(
          sys_clk_freq = int(float(args.sys_clk_freq)),
          **soc_core_argdict(args)
      )
      builder = Builder(soc, **builder_argdict(args))
      builder.build(**vivado_build_argdict(args), run=args.build)
  
      if args.load:
          prog = soc.platform.create_programmer()
          prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"), device=1)
  
  if __name__ == "__main__":
      main()
  
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