new_contents: from liteeth.common import convert_ip
  from liteeth.phy.s7rgmii import LiteEthPHYRGMII
  from liteeth.core import LiteEthUDPIPCore
  from liteeth.frontend.etherbone import LiteEthEtherbone
  
  from targets.mimas_a7.base import BaseSoC
  
  
  class EtherboneSoC(BaseSoC):
      csr_map = {
          "ethphy":  30,
          "ethcore": 31,
      }
      csr_map.update(BaseSoC.csr_map)
  
      def __init__(self,
                   platform,
                   mac_address=0x10e2d5000000,
                   ip_address="192.168.1.50"):
          BaseSoC.__init__(self, platform, cpu_type=None, csr_data_width=32)
  
          # Ethernet PHY and UDP/IP stack
          self.submodules.ethphy = LiteEthPHYRGMII(self.platform.request("eth_clocks"),
                                                   self.platform.request("eth"))
          self.submodules.ethcore = LiteEthUDPIPCore(self.ethphy,
                                                     mac_address,
                                                     convert_ip(ip_address),
                                                     self.clk_freq,
                                                     with_icmp=True)
  
          # Etherbone bridge
          self.add_cpu_or_bridge(LiteEthEtherbone(self.ethcore.udp, 20000))
          self.add_wb_master(self.cpu_or_bridge.master.bus)
  
          self.specials += [
              Keep(self.ethphy.crg.cd_eth_rx.clk),
              Keep(self.ethphy.crg.cd_eth_tx.clk)
          ]
  
          self.platform.add_period_constraint(self.crg.cd_sys.clk, 10.0)
          self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 8.0)
          self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 8.0)
  
          self.platform.add_false_path_constraints(
              self.crg.cd_sys.clk,
              self.ethphy.crg.cd_eth_rx.clk,
              self.ethphy.crg.cd_eth_tx.clk)
  
  
  BaseSoC = EtherboneSoC
  
subject: add bridge_net target