old_contents: #   Copyright (c) 2016, Xilinx, Inc.
  #   All rights reserved.
  # 
  #   Redistribution and use in source and binary forms, with or without 
  #   modification, are permitted provided that the following conditions are met:
  #
  #   1.  Redistributions of source code must retain the above copyright notice, 
  #       this list of conditions and the following disclaimer.
  #
  #   2.  Redistributions in binary form must reproduce the above copyright 
  #       notice, this list of conditions and the following disclaimer in the 
  #       documentation and/or other materials provided with the distribution.
  #
  #   3.  Neither the name of the copyright holder nor the names of its 
  #       contributors may be used to endorse or promote products derived from 
  #       this software without specific prior written permission.
  #
  #   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  #   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 
  #   THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 
  #   PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 
  #   CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
  #   EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 
  #   PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
  #   OR BUSINESS INTERRUPTION). HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
  #   WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 
  #   OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 
  #   ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  
  from .mmio import MMIO
  from .uio import UioController
  from .xlnk import Xlnk
  from .pl import PL
  from .ps import Register
  from .ps import Clocks
  from .gpio import GPIO
  from .devicetree import DeviceTreeSegment
  from .interrupt import Interrupt
  from .bitstream import Bitstream
  from .overlay import Overlay
  from .overlay import DefaultHierarchy
  from .overlay import DefaultIP
  from .pmbus import get_rails
  from .pmbus import DataRecorder
  from .buffer import allocate
  from . import lib
  
  
  __author__ = "Yun Rock Qu"
  __copyright__ = "Copyright 2016, Xilinx"
  __email__ = "pynq_support@xilinx.com"
  
  __all__ = ['lib', 'tests']
  __version__ = '2.5'
  
new_contents: #   Copyright (c) 2016, Xilinx, Inc.
  #   All rights reserved.
  # 
  #   Redistribution and use in source and binary forms, with or without 
  #   modification, are permitted provided that the following conditions are met:
  #
  #   1.  Redistributions of source code must retain the above copyright notice, 
  #       this list of conditions and the following disclaimer.
  #
  #   2.  Redistributions in binary form must reproduce the above copyright 
  #       notice, this list of conditions and the following disclaimer in the 
  #       documentation and/or other materials provided with the distribution.
  #
  #   3.  Neither the name of the copyright holder nor the names of its 
  #       contributors may be used to endorse or promote products derived from 
  #       this software without specific prior written permission.
  #
  #   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  #   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 
  #   THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 
  #   PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 
  #   CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
  #   EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 
  #   PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
  #   OR BUSINESS INTERRUPTION). HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
  #   WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 
  #   OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 
  #   ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  
  from .mmio import MMIO
  from .uio import UioController
  from .xlnk import Xlnk
  from .pl import PL
  from .ps import Register
  from .ps import Clocks
  from .gpio import GPIO
  from .devicetree import DeviceTreeSegment
  from .interrupt import Interrupt
  from .bitstream import Bitstream
  from .overlay import Overlay
  from .overlay import DefaultHierarchy
  from .overlay import DefaultIP
  from .pmbus import get_rails
  from .pmbus import DataRecorder
  from .buffer import allocate
  from .pl_server import Device
  from . import lib
  
  
  __author__ = "Yun Rock Qu"
  __copyright__ = "Copyright 2016, Xilinx"
  __email__ = "pynq_support@xilinx.com"
  
  __all__ = ['lib', 'tests']
  __version__ = '2.5'
  
subject: Add Device class at top-level