from magma import array, wire, compile, EndCircuit
from loam.boards.icestick import IceStick
from mantle.lattice.ice40.RAMB import RAMB

icestick = IceStick()
icestick.Clock.on()
icestick.J1[0].rename('I0').input().on()
icestick.J1[1].rename('I1').input().on()
icestick.J1[2].rename('I2').input().on()
icestick.J1[3].rename('I3').input().on()
icestick.J1[4].rename('I4').input().on()
icestick.J1[5].rename('I5').input().on()
icestick.J1[6].rename('I6').input().on()
icestick.J3[0].rename('D0').output().on()
icestick.J3[1].rename('D1').output().on()

main = icestick.main()
WDATA = array([main.I0, main.I1])
WADDR = array([main.I2, main.I3, 0,0,0,0,0,0,0,0,0])
RADDR = array([main.I4, main.I5, 0,0,0,0,0,0,0,0,0])
WE = main.I6
O = array([main.D0, main.D1])

N = 2
M = 4096//N
rom = M * [0]
for i in range(M):
    rom[i] = i & 0x3

ramb = RAMB( M, N, rom )
#print(ramb.interface)

wire( WE, ramb.WE    )
wire( WADDR, ramb.WADDR )
wire( WDATA, ramb.WDATA )

wire( 1, ramb.RE    )
wire( RADDR, ramb.RADDR )

wire( ramb.RDATA, O)

EndCircuit()
