CRUADD={'add_ro_protocol_base':0x00100000,
'add_ro_prot_conf_reg':0x00100000,
'add_ro_prot_check_mask':0x00100004,
'add_ro_prot_alloc_fail':0x00100008,
'add_ro_prot_ttc_linkerr':0x0010000C,
'add_gbt_wrapper0':0x00400000,
'add_gbt_wrapper1':0x00500000,
'add_gbt_wrapper_gregs':0x00000000,
'add_gbt_wrapper_bank_offset':0x00020000,
'add_gbt_wrapper_atx_pll':0x000E0000,
'add_gbt_wrapper_conf0':0x00000000,
'add_gbt_wrapper_conf1':0x00000004,
'add_gbt_wrapper_test_control':0x00000008,
'add_gbt_wrapper_clk_cnt':0x0000000C,
'add_gbt_wrapper_refclk0_freq':0x00000010,
'add_gbt_wrapper_refclk1_freq':0x00000014,
'add_gbt_wrapper_refclk2_freq':0x00000018,
'add_gbt_wrapper_refclk3_freq':0x0000001C,
'add_gbt_bank_link_offset':0x00002000,
'add_gbt_bank_fpll':0x0000E000,
'add_gbt_link_regs_offset':0x00000000,
'add_gbt_link_xcvr_offset':0x00001000,
'add_gbt_link_status':0x00000000,
'add_gbt_link_txclk_cnt':0x00000004,
'add_gbt_link_rxclk_cnt':0x00000008,
'add_gbt_link_rxframe_32lsb':0x0000000C,
'add_gbt_link_rx_err_cnt':0x00000010,
'add_gbt_link_fec_monitoring':0x0000001C,
'add_gbt_link_mask_hi':0x00000020,
'add_gbt_link_mask_med':0x00000024,
'add_gbt_link_mask_lo':0x00000028,
'add_gbt_link_tx_ctrl_offset':0x0000002C,
'add_gbt_link_source_sel':0x00000030,
'add_gbt_link_clr_errcnt':0x00000038,
'add_gbt_link_rx_ctrl_offset':0x0000003C,
'add_gbt_sc':0x00F00000,
'add_gbt_sca_wr_data':0x00F00000,
'add_gbt_sca_wr_cmd':0x00F00004,
'add_gbt_sca_wr_ctr':0x00F00008,
'add_gbt_sca_rd_data':0x00F00010,
'add_gbt_sca_rd_cmd':0x00F00014,
'add_gbt_sca_rd_ctr':0x00F00018,
'add_gbt_sca_rd_mon':0x00F0001C,
'add_gbt_sca0_wr_data':0x00F00000,
'add_gbt_sca0_wr_cmd':0x00F00004,
'add_gbt_sca0_wr_ctr':0x00F00008,
'add_gbt_sca0_rd_data':0x00F00020,
'add_gbt_sca0_rd_cmd':0x00F00024,
'add_gbt_sca0_rd_ctr':0x00F00028,
'add_gbt_sca0_rd_mon':0x00F0002C,
'add_gbt_sca4_wr_data':0x00F00010,
'add_gbt_sca4_wr_cmd':0x00F00014,
'add_gbt_sca4_wr_ctr':0x00F00018,
'add_gbt_sca4_rd_data':0x00F00030,
'add_gbt_sca4_rd_cmd':0x00F00034,
'add_gbt_sca4_rd_ctr':0x00F00038,
'add_gbt_sca4_rd_mon':0x00F0003C,
'add_gbt_ic_wr_data':0x00F00020,
'add_gbt_ic_wr_cfg':0x00F00024,
'add_gbt_ic_wr_cmd':0x00F00028,
'add_gbt_ic_rd_data':0x00F00030,
'add_gbt_swt_wr_l':0x00F00040,
'add_gbt_swt_wr_m':0x00F00044,
'add_gbt_swt_wr_h':0x00F00048,
'add_gbt_swt_cmd':0x00F0004C,
'add_gbt_swt_rd_l':0x00F00050,
'add_gbt_swt_rd_m':0x00F00054,
'add_gbt_swt_rd_h':0x00F00058,
'add_gbt_swt_mon':0x00F0005C,
'add_gbt_swt_word_mon':0x00F00060,
'add_gbt_sc_link':0x00F00078,
'add_gbt_sc_rst':0x00F0007C,
'add_ttc_pon':0x00200000,
'add_ttc_regs':0x00200000,
'add_ttc_onu':0x00220000,
'add_ttc_clkgen':0x00240000,
'add_ttc_patplayer':0x00260000,
'add_ctp_emu':0x00280000,
'add_ttc_data_ctrl':0x00200000,
'add_ttc_hbtrig_ltu':0x00200004,
'add_ttc_phystrig_ltu':0x00200008,
'add_ttc_eox_sox_ltu':0x0020000C,
'add_ttc_ttcok':0x00200010,
'add_ttc_clkgen_ttc240freq':0x00240000,
'add_ttc_clkgen_glb240freq':0x00240004,
'add_ttc_clkgen_rxref240freq':0x00240008,
'add_ttc_clkgen_txref240freq':0x0024000C,
'add_ttc_clkgen_clkctrl':0x00240010,
'add_ttc_clkgen_clkstat':0x00240014,
'add_ttc_clkgen_pllctrlonu':0x00240018,
'add_ttc_clkgen_pllstatonu':0x0024001C,
'add_ttc_clkgen_phasecnt':0x00240020,
'add_ttc_clkgen_phasestat':0x00240024,
'add_ttc_clkgen_phasehist':0x0024002C,
'add_ttc_clkgen_clknotokcnt':0x00240028,
'add_ttc_clkgen_onufpll':0x00248000,
'add_ttc_onu_ctrl':0x00220000,
'add_pon_verinfo':0x00220000,
'add_pon_wrapper_reg':0x00222000,
'add_pon_wrapper_pll':0x00224000,
'add_pon_wrapper_tx':0x00226000,
'add_onu_user_logic':0x0022A000,
'add_onu_freq_meas':0x0022E000,
'add_patplayer_cfg':0x00260000,
'add_patplayer_idlepat0':0x00260004,
'add_patplayer_idlepat1':0x00260008,
'add_patplayer_idlepat2':0x0026000C,
'add_patplayer_syncpat0':0x00260010,
'add_patplayer_syncpat1':0x00260014,
'add_patplayer_syncpat2':0x00260018,
'add_patplayer_rstpat0':0x0026001C,
'add_patplayer_rstpat1':0x00260020,
'add_patplayer_rstpat2':0x00260024,
'add_patplayer_synccnt':0x00260028,
'add_patplayer_delaycnt':0x0026002C,
'add_patplayer_rstcnt':0x00260030,
'add_patplayer_trigsel':0x00260034,
'add_patplayer_debug':0x00260038,
'add_ctp_emu_core':0x00280000,
'add_ctp_emu_ctrl':0x00280000,
'add_ctp_emu_bc_max':0x00280004,
'add_ctp_emu_hb_max':0x00280008,
'add_ctp_emu_prescaler':0x0028000C,
'add_ctp_emu_runmode':0x00280010,
'add_ctp_emu_physdiv':0x00280014,
'add_ctp_emu_hcdiv':0x00280018,
'add_ctp_emu_userbits':0x0028001C,
'add_ctp_emu_caldiv':0x00280020,
'add_ctp_emu_fbct':0x00280024,
'add_ddg':0x00D00000,
'add_ddg_ctrl':0x00D00000,
'add_ddg_ctrl2':0x00D00004,
'add_ddg_ctrl3':0x00D00008,
'add_ddg_trgmask':0x00D0000C,
'add_ddg_pkt_cnt':0x00D00010,
'add_ddg_trgmiss_cnt':0x00D00014,
'add_base_datapathwrapper0':0x00600000,
'add_base_datapathwrapper1':0x00700000,
'add_dwrapper_gregs':0x00000000,
'add_datapathlink_offset':0x00040000,
'add_flowctrl_offset':0x000C0000,
'add_datalink_offset':0x00002000,
'add_dwrapper_enreg':0x00000000,
'add_dwrapper_datagenctrl':0x00000004,
'add_dwrapper_datagenstatus':0x00000008,
'add_dwrapper_bigfifo_lvl':0x0000000C,
'add_dwrapper_tot_words':0x00000010,
'add_dwrapper_drop_words':0x00000014,
'add_dwrapper_tot_pkts':0x00000018,
'add_dwrapper_drop_pkts':0x0000001C,
'add_dwrapper_lasthbid':0x00000020,
'add_dwrapper_clockcore':0x00000024,
'add_dwrapper_clockcore_free':0x00000028,
'add_dwrapper_tot_per_sec':0x0000002C,
'add_dwrapper_drop_per_sec':0x00000030,
'add_dwrapper_trigsize':0x00000034,
'add_datalink_ctrl':0x00000000,
'add_datalink_rej_pkt':0x00000008,
'add_datalink_acc_pkt':0x0000000C,
'add_datalink_forced_pkt':0x00000010,
'add_flowctrl_ctrlreg':0x00000000,
'add_flowctrl_pkt_rej':0x00000004,
'add_flowctrl_pkt_tot':0x00000008,
'add_serial_flash_csr':0x00A00000,
'add_serial_flash_wr_rst':0x00B00000,
'add_serial_flash_wr_data':0x00B00004,
'add_bsp':0x00000000,
'add_bsp_info':0x00000000,
'add_bsp_hkeeping':0x00010000,
'add_bsp_rsu':0x00020000,
'add_bsp_i2c':0x00030000,
'add_bsp_info_dirtystatus':0x00000000,
'add_bsp_info_shorthash':0x00000004,
'add_bsp_info_builddate':0x00000008,
'add_bsp_info_buildtime':0x0000000C,
'add_bsp_info_boardtype':0x00000010,
'add_bsp_info_userctrl':0x00000018,
'add_bsp_info_usertxsel':0x0000001C,
'add_bsp_hkeeping_gpi':0x00010000,
'add_bsp_hkeeping_gpo':0x00010004,
'add_bsp_hkeeping_tempctrl':0x00010008,
'add_bsp_hkeeping_tempstat':0x00010008,
'add_bsp_hkeeping_swlimit':0x0001000C,
'add_bsp_hkeeping_hwlimit':0x00010010,
'add_bsp_hkeeping_chipid_high':0x00010014,
'add_bsp_hkeeping_chipid_low':0x00010018,
'add_bsp_hkeeping_spare_in':0x0001001C,
'add_bsp_rsu_reconf_cond':0x00020000,
'add_bsp_rsu_watchdog_timeout':0x00020008,
'add_bsp_rsu_watchdog_enable':0x0002000C,
'add_bsp_rsu_pagesel':0x00020010,
'add_bsp_rsu_conf_mode':0x00020014,
'add_bsp_rsu_ctrl':0x00020018,
'add_bsp_i2c_tsensor':0x00030000,
'add_bsp_i2c_cpcie':0x00030100,
'add_bsp_i2c_sfp1':0x00030200,
'add_bsp_i2c_minipods':0x00030300,
'add_bsp_i2c_si5344':0x00030400,
'add_bsp_i2c_si5345_1':0x00030500,
'add_bsp_i2c_si5345_2':0x00030600,
'add_bsp_i2c_sfp2':0x00030700,
'add_bsp_i2c_eeprom':0x00030800,
'add_userlogic':0x00C00000,
'add_userlogic_ctrl':0x00C00000,
'add_pcie_dma_ctrl':0x00000200,
'add_pcie_dma_desc_h':0x00000204,
'add_pcie_dma_desc_l':0x00000208,
'add_pcie_dma_desc_sz':0x0000020C,
'add_pcie_dma_rst':0x00000400,
'add_pcie_dma_ep_id':0x00000500,
'add_pcie_dma_ddg_cfg0':0x00000600,
'add_pcie_dma_ddg_cfg1':0x00000604,
'add_pcie_dma_ddg_cfg2':0x00000608,
'add_pcie_dma_ddg_cfg3':0x0000060C,
'add_pcie_dma_data_sel':0x00000700,
'add_pcie_dma_spg0_ack':0x00000800,
'add_pcie_dma_dbg':0x00000C00,
}
