'''
@Description: 
@version: v0.1
@Author: Ji-Peng
@Date: 2020-07-28 17:36:50
@LastEditTime: 2020-07-28 17:37:42
'''
print("""{a,asd}  ssign ram_res_data_out_corrected_l = first_outside_loop ? {COEFF_WIDTH{1'b0}} : ram_res_data_out_wire_l;""")