A0,A1,A2,A3,A4,A5,A6,A7,A8,B0,B1,B2,B3,B4,B5,B6,B7,B8,C0,C1,C2,C3,C4,C5,C6,C7,C8,E0,E1,E2,E3,E4,E5,E6,E7,E8
PA,PB,PC,Chan3,Chan2,Chan1,Chan0


# ---- START PROCESSING M1 ---- #


# (I0 = NAND2 A0' E0)
Th22 I0_0 A0_0 E0_1
Thand0 I0_1 A0_1 E0_0 A0_0 E0_1

# (I1 = NAND2 A1' E1)
Th22 I1_0 A1_0 E1_1
Thand0 I1_1 A1_1 E1_0 A1_0 E1_1

# (I2 = NAND2 A2' E2)
Th22 I2_0 A2_0 E2_1
Thand0 I2_1 A2_1 E2_0 A2_0 E2_1

# (I3 = NAND2 A3' E3)
Th22 I3_0 A3_0 E3_1
Thand0 I3_1 A3_1 E3_0 A3_0 E3_1

# (I4 = NAND2 A4' E4)
Th22 I4_0 A4_0 E4_1
Thand0 I4_1 A4_1 E4_0 A4_0 E4_1

# (I5 = NAND2 A5' E5)
Th22 I5_0 A5_0 E5_1
Thand0 I5_1 A5_1 E5_0 A5_0 E5_1

# (I6 = NAND2 A6' E6)
Th22 I6_0 A6_0 E6_1
Thand0 I6_1 A6_1 E6_0 A6_0 E6_1

# (I7 = NAND2 A7' E7)
Th22 I7_0 A7_0 E7_1
Thand0 I7_1 A7_1 E7_0 A7_0 E7_1

# (I8 = NAND2 A8' E8)
Th22 I8_0 A8_0 E8_1
Thand0 I8_1 A8_1 E8_0 A8_0 E8_1

# (I9 = AND4 I0 I1 I2 I3)
Th14 I9_0 I0_0 I1_0 I2_0 I3_0
Th44 I9_1 I0_1 I1_1 I2_1 I3_1

# (I10 = AND4 I4 I5 I6 I7)
Th14 I10_0 I4_0 I5_0 I6_0 I7_0
Th44 I10_1 I4_1 I5_1 I6_1 I7_1

# (I11 = AND2 I8 I9)
Thand0 I11_0 I8_0 I9_0 I8_1 I9_1
Th22 I11_1 I8_1 I9_1

# (PA = NAND2 I10 I11)
Th22 PA_0 I10_1 I11_1
Thand0 PA_1 I10_0 I11_0 I10_1 I11_1

# (X10 = XOR2 I0 PA)
Thxor0 X10_0 I0_0 PA_0 I0_1 PA_1
Thxor0 X10_1 I0_0 PA_1 I0_1 PA_0

# (X11 = XOR2 I1 PA)
Thxor0 X11_0 I1_0 PA_0 I1_1 PA_1
Thxor0 X11_1 I1_0 PA_1 I1_1 PA_0

# (X12 = XOR2 I2 PA)
Thxor0 X12_0 I2_0 PA_0 I2_1 PA_1
Thxor0 X12_1 I2_0 PA_1 I2_1 PA_0

# (X13 = XOR2 I3 PA)
Thxor0 X13_0 I3_0 PA_0 I3_1 PA_1
Thxor0 X13_1 I3_0 PA_1 I3_1 PA_0

# (X14 = XOR2 I4 PA)
Thxor0 X14_0 I4_0 PA_0 I4_1 PA_1
Thxor0 X14_1 I4_0 PA_1 I4_1 PA_0

# (X15 = XOR2 I5 PA)
Thxor0 X15_0 I5_0 PA_0 I5_1 PA_1
Thxor0 X15_1 I5_0 PA_1 I5_1 PA_0

# (X16 = XOR2 I6 PA)
Thxor0 X16_0 I6_0 PA_0 I6_1 PA_1
Thxor0 X16_1 I6_0 PA_1 I6_1 PA_0

# (X17 = XOR2 I7 PA)
Thxor0 X17_0 I7_0 PA_0 I7_1 PA_1
Thxor0 X17_1 I7_0 PA_1 I7_1 PA_0

# (X18 = XOR2 I8 PA)
Thxor0 X18_0 I8_0 PA_0 I8_1 PA_1
Thxor0 X18_1 I8_0 PA_1 I8_1 PA_0


# ---- DONE PROCESSING M1 ---- #


# ---- START PROCESSING M2 ---- #


# (I12 = NOR2 E0' B0)
Thand0 I12_0 E0_0 B0_1 E0_1 B0_0
Th22 I12_1 E0_1 B0_0

# (I13 = NOR2 E1' B1)
Thand0 I13_0 E1_0 B1_1 E1_1 B1_0
Th22 I13_1 E1_1 B1_0

# (I14 = NOR2 E2' B2)
Thand0 I14_0 E2_0 B2_1 E2_1 B2_0
Th22 I14_1 E2_1 B2_0

# (I15 = NOR2 E3' B3)
Thand0 I15_0 E3_0 B3_1 E3_1 B3_0
Th22 I15_1 E3_1 B3_0

# (I16 = NOR2 E4' B4)
Thand0 I16_0 E4_0 B4_1 E4_1 B4_0
Th22 I16_1 E4_1 B4_0

# (I17 = NOR2 E5' B5)
Thand0 I17_0 E5_0 B5_1 E5_1 B5_0
Th22 I17_1 E5_1 B5_0

# (I18 = NOR2 E6' B6)
Thand0 I18_0 E6_0 B6_1 E6_1 B6_0
Th22 I18_1 E6_1 B6_0

# (I19 = NOR2 E7' B7)
Thand0 I19_0 E7_0 B7_1 E7_1 B7_0
Th22 I19_1 E7_1 B7_0

# (I20 = NOR2 E8' B8)
Thand0 I20_0 E8_0 B8_1 E8_1 B8_0
Th22 I20_1 E8_1 B8_0

# (I21 = NAND2 I12 X10)
Th22 I21_0 I12_1 X10_1
Thand0 I21_1 I12_0 X10_0 I12_1 X10_1

# (I22 = NAND2 I13 X11)
Th22 I22_0 I13_1 X11_1
Thand0 I22_1 I13_0 X11_0 I13_1 X11_1

# (I23 = NAND2 I14 X12)
Th22 I23_0 I14_1 X12_1
Thand0 I23_1 I14_0 X12_0 I14_1 X12_1

# (I24 = NAND2 I15 X13)
Th22 I24_0 I15_1 X13_1
Thand0 I24_1 I15_0 X13_0 I15_1 X13_1

# (I25 = NAND2 I16 X14)
Th22 I25_0 I16_1 X14_1
Thand0 I25_1 I16_0 X14_0 I16_1 X14_1

# (I26 = NAND2 I17 X15)
Th22 I26_0 I17_1 X15_1
Thand0 I26_1 I17_0 X15_0 I17_1 X15_1

# (I27 = NAND2 I18 X16)
Th22 I27_0 I18_1 X16_1
Thand0 I27_1 I18_0 X16_0 I18_1 X16_1

# (I28 = NAND2 I19 X17)
Th22 I28_0 I19_1 X17_1
Thand0 I28_1 I19_0 X17_0 I19_1 X17_1

# (I29 = NAND2 I20 X18)
Th22 I29_0 I20_1 X18_1
Thand0 I29_1 I20_0 X18_0 I20_1 X18_1

# (I30 = AND4 I21 I22 I23 I24)
Th14 I30_0 I21_0 I22_0 I23_0 I24_0
Th44 I30_1 I21_1 I22_1 I23_1 I24_1

# (I31 = AND4 I25 I26 I27 I28)
Th14 I31_0 I25_0 I26_0 I27_0 I28_0
Th44 I31_1 I25_1 I26_1 I27_1 I28_1

# (I32 = AND2 I29 I30)
Thand0 I32_0 I29_0 I30_0 I29_1 I30_1
Th22 I32_1 I29_1 I30_1

# (PB = NAND2 I31 I32)
Th22 PB_0 I31_1 I32_1
Thand0 PB_1 I31_0 I32_0 I31_1 I32_1

# (X20 = XOR2 I21 PB)
Thxor0 X20_0 I21_0 PB_0 I21_1 PB_1
Thxor0 X20_1 I21_0 PB_1 I21_1 PB_0

# (X21 = XOR2 I22 PB)
Thxor0 X21_0 I22_0 PB_0 I22_1 PB_1
Thxor0 X21_1 I22_0 PB_1 I22_1 PB_0

# (X22 = XOR2 I23 PB)
Thxor0 X22_0 I23_0 PB_0 I23_1 PB_1
Thxor0 X22_1 I23_0 PB_1 I23_1 PB_0

# (X23 = XOR2 I24 PB)
Thxor0 X23_0 I24_0 PB_0 I24_1 PB_1
Thxor0 X23_1 I24_0 PB_1 I24_1 PB_0

# (X24 = XOR2 I25 PB)
Thxor0 X24_0 I25_0 PB_0 I25_1 PB_1
Thxor0 X24_1 I25_0 PB_1 I25_1 PB_0

# (X25 = XOR2 I26 PB)
Thxor0 X25_0 I26_0 PB_0 I26_1 PB_1
Thxor0 X25_1 I26_0 PB_1 I26_1 PB_0

# (X26 = XOR2 I27 PB)
Thxor0 X26_0 I27_0 PB_0 I27_1 PB_1
Thxor0 X26_1 I27_0 PB_1 I27_1 PB_0

# (X27 = XOR2 I28 PB)
Thxor0 X27_0 I28_0 PB_0 I28_1 PB_1
Thxor0 X27_1 I28_0 PB_1 I28_1 PB_0

# (X28 = XOR2 I29 PB)
Thxor0 X28_0 I29_0 PB_0 I29_1 PB_1
Thxor0 X28_1 I29_0 PB_1 I29_1 PB_0


# ---- DONE PROCESSING M2 ---- #


# ---- START PROCESSING M3 ---- #


# (I33 = NOR2 E0' C0)
Thand0 I33_0 E0_0 C0_1 E0_1 C0_0
Th22 I33_1 E0_1 C0_0

# (I34 = NOR2 E1' C1)
Thand0 I34_0 E1_0 C1_1 E1_1 C1_0
Th22 I34_1 E1_1 C1_0

# (I35 = NOR2 E2' C2)
Thand0 I35_0 E2_0 C2_1 E2_1 C2_0
Th22 I35_1 E2_1 C2_0

# (I36 = NOR2 E3' C3)
Thand0 I36_0 E3_0 C3_1 E3_1 C3_0
Th22 I36_1 E3_1 C3_0

# (I37 = NOR2 E4' C4)
Thand0 I37_0 E4_0 C4_1 E4_1 C4_0
Th22 I37_1 E4_1 C4_0

# (I38 = NOR2 E5' C5)
Thand0 I38_0 E5_0 C5_1 E5_1 C5_0
Th22 I38_1 E5_1 C5_0

# (I39 = NOR2 E6' C6)
Thand0 I39_0 E6_0 C6_1 E6_1 C6_0
Th22 I39_1 E6_1 C6_0

# (I40 = NOR2 E7' C7)
Thand0 I40_0 E7_0 C7_1 E7_1 C7_0
Th22 I40_1 E7_1 C7_0

# (I41 = NOR2 E8' C8)
Thand0 I41_0 E8_0 C8_1 E8_1 C8_0
Th22 I41_1 E8_1 C8_0

# (I43 = NAND3 X10 X20 I33)
Th33 I43_0 X10_1 X20_1 I33_1
Th13 I43_1 X10_0 X20_0 I33_0

# (I45 = NAND3 X11 X21 I34)
Th33 I45_0 X11_1 X21_1 I34_1
Th13 I45_1 X11_0 X21_0 I34_0

# (I47 = NAND3 X12 X22 I35)
Th33 I47_0 X12_1 X22_1 I35_1
Th13 I47_1 X12_0 X22_0 I35_0

# (I49 = NAND3 X13 X23 I36)
Th33 I49_0 X13_1 X23_1 I36_1
Th13 I49_1 X13_0 X23_0 I36_0

# (I51 = NAND3 X14 X24 I37)
Th33 I51_0 X14_1 X24_1 I37_1
Th13 I51_1 X14_0 X24_0 I37_0

# (I53 = NAND3 X15 X25 I38)
Th33 I53_0 X15_1 X25_1 I38_1
Th13 I53_1 X15_0 X25_0 I38_0

# (I55 = NAND3 X16 X26 I39)
Th33 I55_0 X16_1 X26_1 I39_1
Th13 I55_1 X16_0 X26_0 I39_0

# (I57 = NAND3 X17 X27 I40)
Th33 I57_0 X17_1 X27_1 I40_1
Th13 I57_1 X17_0 X27_0 I40_0

# (I59 = NAND3 X18 X28 I41)
Th33 I59_0 X18_1 X28_1 I41_1
Th13 I59_1 X18_0 X28_0 I41_0

# (I60 = AND2 I43 I45)
Thand0 I60_0 I43_0 I45_0 I43_1 I45_1
Th22 I60_1 I43_1 I45_1

# (I61 = AND2 I47 I49)
Thand0 I61_0 I47_0 I49_0 I47_1 I49_1
Th22 I61_1 I47_1 I49_1

# (I62 = AND2 I51 I53)
Thand0 I62_0 I51_0 I53_0 I51_1 I53_1
Th22 I62_1 I51_1 I53_1

# (I63 = AND2 I55 I57)
Thand0 I63_0 I55_0 I57_0 I55_1 I57_1
Th22 I63_1 I55_1 I57_1

# (I64 = AND2 I60 I61)
Thand0 I64_0 I60_0 I61_0 I60_1 I61_1
Th22 I64_1 I60_1 I61_1

# (I65 = AND2 I62 I63)
Thand0 I65_0 I62_0 I63_0 I62_1 I63_1
Th22 I65_1 I62_1 I63_1

# (I66 = AND2 I64 I65)
Thand0 I66_0 I64_0 I65_0 I64_1 I65_1
Th22 I66_1 I64_1 I65_1

# (PC = NAND2 I59 I66)
Th22 PC_0 I59_1 I66_1
Thand0 PC_1 I59_0 I66_0 I59_1 I66_1


# ---- DONE PROCESSING M3 ---- #


# ---- START PROCESSING M4 ---- #


# (I67 = NAND2 A0 PA)
Th22 I67_0 A0_1 PA_1
Thand0 I67_1 A0_0 PA_0 A0_1 PA_1

# (I68 = NAND2 A1 PA)
Th22 I68_0 A1_1 PA_1
Thand0 I68_1 A1_0 PA_0 A1_1 PA_1

# (I69 = NAND2 A2 PA)
Th22 I69_0 A2_1 PA_1
Thand0 I69_1 A2_0 PA_0 A2_1 PA_1

# (I70 = NAND2 A3 PA)
Th22 I70_0 A3_1 PA_1
Thand0 I70_1 A3_0 PA_0 A3_1 PA_1

# (I71 = NAND2 A4 PA)
Th22 I71_0 A4_1 PA_1
Thand0 I71_1 A4_0 PA_0 A4_1 PA_1

# (I72 = NAND2 A5 PA)
Th22 I72_0 A5_1 PA_1
Thand0 I72_1 A5_0 PA_0 A5_1 PA_1

# (I73 = NAND2 A6 PA)
Th22 I73_0 A6_1 PA_1
Thand0 I73_1 A6_0 PA_0 A6_1 PA_1

# (I74 = NAND2 A7 PA)
Th22 I74_0 A7_1 PA_1
Thand0 I74_1 A7_0 PA_0 A7_1 PA_1

# (I75 = NAND2 A8 PA)
Th22 I75_0 A8_1 PA_1
Thand0 I75_1 A8_0 PA_0 A8_1 PA_1

# (I76 = NAND2 B0 PB)
Th22 I76_0 B0_1 PB_1
Thand0 I76_1 B0_0 PB_0 B0_1 PB_1

# (I77 = NAND2 B1 PB)
Th22 I77_0 B1_1 PB_1
Thand0 I77_1 B1_0 PB_0 B1_1 PB_1

# (I78 = NAND2 B2 PB)
Th22 I78_0 B2_1 PB_1
Thand0 I78_1 B2_0 PB_0 B2_1 PB_1

# (I79 = NAND2 B3 PB)
Th22 I79_0 B3_1 PB_1
Thand0 I79_1 B3_0 PB_0 B3_1 PB_1

# (I80 = NAND2 B4 PB)
Th22 I80_0 B4_1 PB_1
Thand0 I80_1 B4_0 PB_0 B4_1 PB_1

# (I81 = NAND2 B5 PB)
Th22 I81_0 B5_1 PB_1
Thand0 I81_1 B5_0 PB_0 B5_1 PB_1

# (I82 = NAND2 B6 PB)
Th22 I82_0 B6_1 PB_1
Thand0 I82_1 B6_0 PB_0 B6_1 PB_1

# (I83 = NAND2 B7 PB)
Th22 I83_0 B7_1 PB_1
Thand0 I83_1 B7_0 PB_0 B7_1 PB_1

# (I84 = NAND2 B8 PB)
Th22 I84_0 B8_1 PB_1
Thand0 I84_1 B8_0 PB_0 B8_1 PB_1

# (I85 = NAND2 C0 PC)
Th22 I85_0 C0_1 PC_1
Thand0 I85_1 C0_0 PC_0 C0_1 PC_1

# (I86 = NAND2 C1 PC)
Th22 I86_0 C1_1 PC_1
Thand0 I86_1 C1_0 PC_0 C1_1 PC_1

# (I87 = NAND2 C2 PC)
Th22 I87_0 C2_1 PC_1
Thand0 I87_1 C2_0 PC_0 C2_1 PC_1

# (I88 = NAND2 C3 PC)
Th22 I88_0 C3_1 PC_1
Thand0 I88_1 C3_0 PC_0 C3_1 PC_1

# (I89 = NAND2 C4 PC)
Th22 I89_0 C4_1 PC_1
Thand0 I89_1 C4_0 PC_0 C4_1 PC_1

# (I90 = NAND2 C5 PC)
Th22 I90_0 C5_1 PC_1
Thand0 I90_1 C5_0 PC_0 C5_1 PC_1

# (I91 = NAND2 C6 PC)
Th22 I91_0 C6_1 PC_1
Thand0 I91_1 C6_0 PC_0 C6_1 PC_1

# (I92 = NAND2 C7 PC)
Th22 I92_0 C7_1 PC_1
Thand0 I92_1 C7_0 PC_0 C7_1 PC_1

# (I93 = NAND2 C8 PC)
Th22 I93_0 C8_1 PC_1
Thand0 I93_1 C8_0 PC_0 C8_1 PC_1

# I67 = APA[0]
# I76 = BPB[0]
# I85 = CPC[0]

# (I96 = NAND4 E0 I67 I76 I85)
# (I94 = AND2 E0 I67)
Thand0 I94_0 E0_0 I67_0 E0_1 I67_1
Th22 I94_1 E0_1 I67_1

# (I95 = AND2 I76 I85)
Thand0 I95_0 I76_0 I85_0 I76_1 I85_1
Th22 I95_1 I76_1 I85_1

# (I96 = NAND2 I94 I95)
Th22 I96_0 I94_1 I95_1
Thand0 I96_1 I94_0 I95_0 I94_1 I95_1

# (I99 = NAND4 E1 I68 I77 I86)
# (I97 = AND2 E1 I68)
Thand0 I97_0 E1_0 I68_0 E1_1 I68_1
Th22 I97_1 E1_1 I68_1

# (I98 = AND2 I77 I86)
Thand0 I98_0 I77_0 I86_0 I77_1 I86_1
Th22 I98_1 I77_1 I86_1

# (I99 = NAND2 I97 I98)
Th22 I99_0 I97_1 I98_1
Thand0 I99_1 I97_0 I98_0 I97_1 I98_1

# (I102 = NAND4 E2 I69 I78 I87)
# (I100 = AND2 E2 I69)
Thand0 I100_0 E2_0 I69_0 E2_1 I69_1
Th22 I100_1 E2_1 I69_1

# (I101 = AND2 I78 I87)
Thand0 I101_0 I78_0 I87_0 I78_1 I87_1
Th22 I101_1 I78_1 I87_1

# (I102 = NAND2 I100 I101)
Th22 I102_0 I100_1 I101_1
Thand0 I102_1 I100_0 I101_0 I100_1 I101_1

# (I105 = NAND4 E3 I70 I79 I88)
# (I103 = AND2 E3 I70)
Thand0 I103_0 E3_0 I70_0 E3_1 I70_1
Th22 I103_1 E3_1 I70_1

# (I104 = AND2 I79 I88)
Thand0 I104_0 I79_0 I88_0 I79_1 I88_1
Th22 I104_1 I79_1 I88_1

# (I105 = NAND2 I103 I104)
Th22 I105_0 I103_1 I104_1
Thand0 I105_1 I103_0 I104_0 I103_1 I104_1

# (I108 = NAND4 E4 I71 I80 I89)
# (I106 = AND2 E4 I71)
Thand0 I106_0 E4_0 I71_0 E4_1 I71_1
Th22 I106_1 E4_1 I71_1

# (I107 = AND2 I80 I89)
Thand0 I107_0 I80_0 I89_0 I80_1 I89_1
Th22 I107_1 I80_1 I89_1

# (I108 = NAND2 I106 I107)
Th22 I108_0 I106_1 I107_1
Thand0 I108_1 I106_0 I107_0 I106_1 I107_1

# (I111 = NAND4 E5 I72 I81 I90)
# (I109 = AND2 E5 I72)
Thand0 I109_0 E5_0 I72_0 E5_1 I72_1
Th22 I109_1 E5_1 I72_1

# (I110 = AND2 I81 I90)
Thand0 I110_0 I81_0 I90_0 I81_1 I90_1
Th22 I110_1 I81_1 I90_1

# (I111 = NAND2 I109 I110)
Th22 I111_0 I109_1 I110_1
Thand0 I111_1 I109_0 I110_0 I109_1 I110_1

# (I114 = NAND4 E6 I73 I82 I91)
# (I112 = AND2 E6 I73)
Thand0 I112_0 E6_0 I73_0 E6_1 I73_1
Th22 I112_1 E6_1 I73_1

# (I113 = AND2 I82 I91)
Thand0 I113_0 I82_0 I91_0 I82_1 I91_1
Th22 I113_1 I82_1 I91_1

# (I114 = NAND2 I112 I113)
Th22 I114_0 I112_1 I113_1
Thand0 I114_1 I112_0 I113_0 I112_1 I113_1

# (I117 = NAND4 E7 I74 I83 I92)
# (I115 = AND2 E7 I74)
Thand0 I115_0 E7_0 I74_0 E7_1 I74_1
Th22 I115_1 E7_1 I74_1

# (I116 = AND2 I83 I92)
Thand0 I116_0 I83_0 I92_0 I83_1 I92_1
Th22 I116_1 I83_1 I92_1

# (I117 = NAND2 I115 I116)
Th22 I117_0 I115_1 I116_1
Thand0 I117_1 I115_0 I116_0 I115_1 I116_1

# (I120 = NAND4 E8 I75 I84 I93)
# (I118 = AND2 E8 I75)
Thand0 I118_0 E8_0 I75_0 E8_1 I75_1
Th22 I118_1 E8_1 I75_1

# (I119 = AND2 I84 I93)
Thand0 I119_0 I84_0 I93_0 I84_1 I93_1
Th22 I119_1 I84_1 I93_1

# (I120 = NAND2 I118 I119)
Th22 I120_0 I118_1 I119_1
Thand0 I120_1 I118_0 I119_0 I118_1 I119_1


# ---- DONE PROCESSING M4 ---- #


# ---- START PROCESSING M5 ---- #

# I96 = I[0]
# I99 = I[1]
# I102 = I[2]
# I105 = I[3]
# I108 = I[4]
# I111 = I[5]
# I114 = I[6]
# I117 = I[7]
# I120 = I[8]


# ---- START CHAN3 Processing ---- #


# (I121 = AND4 I96 I99 I102 I105)
Th14 I121_0 I96_0 I99_0 I102_0 I105_0
Th44 I121_1 I96_1 I99_1 I102_1 I105_1

# (I122 = AND4 I108 I111 I114 I117)
Th14 I122_0 I108_0 I111_0 I114_0 I117_0
Th44 I122_1 I108_1 I111_1 I114_1 I117_1

# (I123 = AND2 I121 I122)
Thand0 I123_0 I121_0 I122_0 I121_1 I122_1
Th22 I123_1 I121_1 I122_1

# (Chan3 = NOR2 I120' I123)
Th22 Chan3_0 I120_1 I123_0
Thand0 Chan3_1 I120_0 I123_1 I120_1 I123_0


# ---- DONE CHAN3 Processing ---- #


# ---- START CHAN2 Processing ---- #


# (I124 = NAND2 I111' I114)
Th22 I124_0 I111_0 I114_1
Thand0 I124_1 I111_1 I114_0 I111_0 I114_1

# (Chan2 = NAND4 I108 I114 I117 I124)
# (I125 = AND2 I108 I114)
Thand0 I125_0 I108_0 I114_0 I108_1 I114_1
Th22 I125_1 I108_1 I114_1

# (I126 = AND2 I117 I124)
Thand0 I126_0 I117_0 I124_0 I117_1 I124_1
Th22 I126_1 I117_1 I124_1

# (Chan2 = NAND2 I125 I126)
Th22 Chan2_0 I125_1 I126_1
Thand0 Chan2_1 I125_0 I126_0 I125_1 I126_1


# ---- DONE CHAN2 Processing ---- #


# ---- START CHAN1 Processing ---- #


# (I128 = NAND3 I102' I108 I111)
# (I127 = AND2 I102' I108)
Thand0 I127_0 I102_1 I108_0 I102_0 I108_1
Th22 I127_1 I102_0 I108_1

# (I128 = NAND2 I111 I127)
Th22 I128_0 I111_1 I127_1
Thand0 I128_1 I111_0 I127_0 I111_1 I127_1

# (I131 = NAND4 I105 I108 I111 I114)
# (I129 = AND2 I105 I108)
Thand0 I129_0 I105_0 I108_0 I105_1 I108_1
Th22 I129_1 I105_1 I108_1

# (I130 = AND2 I111 I114)
Thand0 I130_0 I111_0 I114_0 I111_1 I114_1
Th22 I130_1 I111_1 I114_1

# (I131 = NAND2 I129 I130)
Th22 I131_0 I129_1 I130_1
Thand0 I131_1 I129_0 I130_0 I129_1 I130_1

# (Chan1 = NAND4 I114 I117 I128 I131)
# (I132 = AND2 I114 I117)
Thand0 I132_0 I114_0 I117_0 I114_1 I117_1
Th22 I132_1 I114_1 I117_1

# (I133 = AND2 I128 I131)
Thand0 I133_0 I128_0 I131_0 I128_1 I131_1
Th22 I133_1 I128_1 I131_1

# (Chan1 = NAND2 I132 I133)
Th22 Chan1_0 I132_1 I133_1
Thand0 Chan1_1 I132_0 I133_0 I132_1 I133_1


# ---- DONE CHAN1 Processing ---- #


# ---- START CHAN0 Processing ---- #


# (I136 = NAND4 I99' I102 I111 I114)
# (I134 = AND2 I99' I102)
Thand0 I134_0 I99_1 I102_0 I99_0 I102_1
Th22 I134_1 I99_0 I102_1

# (I135 = AND2 I111 I114)
Thand0 I135_0 I111_0 I114_0 I111_1 I114_1
Th22 I135_1 I111_1 I114_1

# (I136 = NAND2 I134 I135)
Th22 I136_0 I134_1 I135_1
Thand0 I136_1 I134_0 I135_0 I134_1 I135_1

# (Chan0 = NAND4 I117 I124 I131 I136)
# (I137 = AND2 I117 I124)
Thand0 I137_0 I117_0 I124_0 I117_1 I124_1
Th22 I137_1 I117_1 I124_1

# (I138 = AND2 I131 I136)
Thand0 I138_0 I131_0 I136_0 I131_1 I136_1
Th22 I138_1 I131_1 I136_1

# (Chan0 = NAND2 I137 I138)
Th22 Chan0_0 I137_1 I138_1
Thand0 Chan0_1 I137_0 I138_0 I137_1 I138_1


# ---- DONE CHAN0 Processing ---- #


# ---- DONE PROCESSING M5 ---- #
