import magma as m
from loam.parts.xilinx.spartan3 import XC3S250E
from loam.parts.generic.crystal import Crystal
#from loam.parts.ftdi.ft232r import FT232R
#from loam.peripherals.timer import Timer

from .papilio import Papilio

'''
SPECS: Xilinx XC3S250E
----------------------------------
Logics Cells               : 5508
CLBs                       : 612
Distributed RAM bits       : 38K
Block RAM bits             : 216K
DCMs                       : 4
Max User I/O               : 172
Max Differential I/O Pairs : 68
----------------------------------
'''

#
# UCF file for the Papilio One board
# Generated by pin_converter, written by Kevin Lindsey
# https://github.com/thelonious/papilio_pins/tree/development/pin_converter

# Main board wing pin [] to FPGA pin Pxx map
# -------C-------    -------B-------    -------A-------
# [GND] [C00] P91    [GND] [B00] P85    P86 [A15]
# [2V5] [C01] P92    [2V5] [B01] P83    P84 [A14]
# [3V3] [C02] P94    [3V3] [B02] P78    P79 [A13]
# [5V0] [C03] P95    [5V0] [B03] P71    P70 [A12]
#       [C04] P98          [B04] P68    P67 [A11] [5V0]
#       [C05] P2           [B05] P66    P65 [A10] [3V3]
#       [C06] P3           [B06] P63    P62 [A09] [2V5]
#       [C07] P4           [B07] P61    P60 [A08] [GND]
# [GND] [C08] P5     [GND] [B08] P58    P57 [A07]
# [2V5] [C09] P9     [2V5] [B09] P54    P53 [A06]
# [3V3] [C10] P10    [3V3] [B10] P41    P40 [A05]
# [5V0] [C11] P11    [5V0] [B11] P36    P35 [A04]
#       [C12] P12          [B12] P34    P33 [A03] [5V0]
#       [C13] P15          [B13] P32    P26 [A02] [3V3]
#       [C14] P16          [B14] P25    P23 [A01] [2V5]
#       [C15] P17          [B15] P22    P18 [A00] [GND]
#
class PapilioOne(Papilio):

    def __init__(self, fpga=XC3S250E):
        super(PapilioOne,self).__init__("PapilioOne")

        # Need to define the interface ...

        self.fpga = fpga = fpga(board=self)

        self.A = [fpga.P18, fpga.P23, fpga.P26, fpga.P33, 
                  fpga.P35, fpga.P40, fpga.P53, fpga.P57,
                  fpga.P60, fpga.P62, fpga.P65, fpga.P67, 
                  fpga.P70, fpga.P79, fpga.P84, fpga.P86]

        self.B = [fpga.P85, fpga.P83, fpga.P78, fpga.P71, 
                  fpga.P68, fpga.P66, fpga.P63, fpga.P61,
                  fpga.P58, fpga.P54, fpga.P41, fpga.P36, 
                  fpga.P34, fpga.P32, fpga.P25, fpga.P22]

        self.C = [fpga.P91, fpga.P92, fpga.P94, fpga.P95, 
                  fpga.P98, fpga.P2,  fpga.P3,  fpga.P4,
                  fpga.P5,  fpga.P9,  fpga.P10, fpga.P11,
                  fpga.P12, fpga.P15, fpga.P16, fpga.P17]

        # Clock setup
        self.CLKIN = fpga.P89
        self.CLKIN.rename('CLKIN')

        #print('wiring crystal')
        self.Crystal = Crystal(32000000, board=self)
        m.wire(self.Crystal.O, self.CLKIN.I)

        #print('wiring clock')
        self.Clock = fpga.clock
        m.wire(self.CLKIN.O, self.Clock.I)


        # Timer peripheral setup
        #print('wiring timer')
        # self.Timer = Timer(fpga, name='systimer')


        # USART setup
        self.RX = fpga.P88
        self.RX.rename('RX').input()

        self.TX = fpga.P90
        self.TX.rename('TX').output()

        #print('wiring uart')
        #self.usart = FT232R(board=self)
        #m.wire(self.TX, self.usart.RX)
        #m.wire(self.usart.TX, self.RX)

        #self.usart0 = fpga.USART(fpga)
        #self.usart.peripheral(self.usart0)
        #m.wire(self.usart0.TX, self.TX)
        #m.wire(self.RX, self.usart0.RX)


        # Flash setup
        #self.CS   = fpga.P24
        #self.SCLK = fpga.P50
        #self.MOSI = fpga.P27
        #self.MISO = fpga.P44

        #self.Flash = Flash(self)
        #self.SCLK.rename('SCLK').output()
        #self.MOSI.rename('MOSI').output()
        #self.MISO.rename('MISO').output()
        #self.CS.  rename('CS')  .output()
        #m.wire(self.SCLK, self.Flash.SCLK)
        #m.wire(self.MOSI, self.Flash.MOSI)
        #m.wire(self.Flash.MISO, self.MISO)
        #m.wire(self.CS, self.Flash.CS)

